Datasheet

Section 10 I/O Ports
Page 612 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
• Modes 3 and 7
EXPE 1 0
A21E 0 1 ⎯
SSU settings (1) in table
below
(2) in
table
below
(3) in
table
below
⎯ ⎯ (1) in table
below
(2) in
table
below
(3) in
table
below
PA5DDR 0 1 0*
4
⎯ 0 1 0 1 0*
4
⎯
PA5
input
PA5
output
SSCK0-B
input
*
2
*
5
SSCK0-B
output
*
3
*
5
PA5
input
A21
output
PA5
input
PA5
output
SSCK0-B
input
*
2
*
5
SSCK0-B
output
*
3
*
5
Pin function
IRQ5-A interrupt input*
1
Notes: 1. IRQ5-A input when the ITS5 bit in ITSR is 0.
2. When using as SSCK0-B input, set SSCK0S1 and SSCK0S0 in PFCR5 to B'01 before
other register setting.
3. When using as SSCK0-B output, set SSCK0S1 and SSCK0S0 in PFCR5 to B'01 before
other register setting.
4. PA5DDR = 0 when the SSU pin is used as input.
5. Do not set up for SSU unless SSCK0S1 and SSCK0S0 = B'01 in PFCR5.
Use as I/O port.
SSU settings (1) (2) (1) (3) (1) (2) (1) (3)
SSUMS 0 1
MSS 0 1 0 1
SCKS 0 1 0 1 0 1 0 1
Pin state ⎯ SSCK
input
⎯ SSCK
output
⎯ SSCK
input
⎯ SSCK
output
[Legend]
⎯: Not used as the SSU pin (can be used as an I/O port).
Note: See tables 20.4 to 20.6.