Datasheet

Section 1 Overview
Page 34 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Pin No.
H8S/2456, H8S/2456R
H8S/2454
Type Symbol PLQP0144KA-A
PTLG0145JB-A
PLQP0120LA-A,
PLQP0120KA-A I/O Function
XTAL 96 F12 81 Input For connection to a crystal
oscillator. See section 23, Clock
Pulse Generator, for typical
connection diagrams for a crystal
resonator and external clock input.
EXTAL 97 F13 82 Input For connection to a crystal
oscillator. The EXTAL pin can also
input an external clock. See section
23, Clock Pulse Generator, for
typical connection diagrams for a
crystal resonator and external clock
input.
 94 F10 79 Output Supplies the system clock to
external devices.
Clock
SDRAM
*
1
36 M1 ⎯ Output When a synchronous DRAM is
connected, this pin is connected to
the CLK pin of the synchronous
DRAM. For details, see section 6,
Bus Controller (BSC).
Operating
mode
control
MD2
MD1
MD0
1
144
143
B1
A2
A3
1
120
119
Input These pins set the operating mode.
These pins should not be changed
during operation.
System
control
RES 92 G11 77 Input Reset pin. When this pin is driven
low, the chip is reset.
STBY 103 D13 88 Input When this pin is driven low, a
transition is made to hardware
standby mode.
EMLE 32 K1 30 Input On-chip emulator enable pin. When
the on-chip emulator is used, this
pin should be fixed high. At this
time, pins P53, PG4 to PG6, and
WDTOVF are used exclusively by
the on-chip emulator. Therefore, the
corresponding pin functions of those
pins are not available. When the on-
chip emulator is not used, this pin
should be fixed low.