Datasheet

Section 10 I/O Ports
Page 590 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
10.7.4 Port 8 Open Drain Control Register (P8ODR)
P8ODR specifies the output type of each port 8 pin.
Bit Bit Name Initial Value R/W Description
7, 6 ⎯ All 0 ⎯ Reserved
These bits are always read as 0. Only the initial
values should be written to these bits.
5 P85ODR 0 R/W
4 P84ODR 0 R/W
3 P83ODR 0 R/W
2 P82ODR 0 R/W
1 P81ODR 0 R/W
0 P80ODR 0 R/W
Setting a P8ODR bit to 1 makes the corresponding
pin an NMOS open-drain output pin, while clearing
a P8ODR bit to 0 makes the corresponding pin a
CMOS output pin.
Bits 4, 2, and 0 are reserved in the H8S/2454
Group.
10.7.5 Pin Functions
Port 8 pins also function as SCI I/Os, interrupt inputs, EXDMAC I/Os, PPG outputs, TPU I/Os,
and 8-bit timer I/Os. The correspondence between the register specification and the pin functions
is shown below.
(1) Pin Functions of H8S/2456 Group and H8S/2456R Group
• P85/EDACK3/IRQ5-B/SCK3/PO5-B/TIOCB4-B/TMO1-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to
IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0 in TCSR_1 of the
8-bit timer, bit NDER5 in NDERL of PPG, bit AMS in EDMDR_3 of EXDMAC, bit C/A in
SMR_3 and bits CKE0 and CKE1 in SCR_3 of SCI, bits PPGS, TPUS, and TMRS in PFCR3,
bit P85DDR, and bit ITS5 in ITSR of the interrupt controller.