Datasheet

Section 10 I/O Ports
Page 576 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
• Modes 3 and 7 (EXPE = 0)
BRLE
BACKS
⎯
TPU channel 4
settings
(1) in table
below
(2) in table
below
OS3 to OS0 ⎯ All 0 Not all 0
CKE1 ⎯ 0 1 ⎯
C/A ⎯ 0 1 ⎯ ⎯
CKE0 ⎯ 0 1 ⎯ ⎯ ⎯
P52DDR ⎯ 0 1 1 ⎯ ⎯ ⎯ ⎯
NDER4 ⎯ ⎯ 0 1 ⎯ ⎯ ⎯ ⎯
P52
input
P52
output
PO4-B
output*
4
SCK2
output
SCK2
output
SCK2
input
TMO0-B
output*
6
TIOCA4-B
output*
5
TIOCA4-B input*
1
*
5
Pin function
IRQ2-A interrupt input*
2
TPU channel 4
settings
(2) (1) (1) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'001x B'0011
IOBA to IOA0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
Other than
B'xx00
B'xx00 Other than B'xx00
CCLR1,
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'10
B'10
Output function ⎯ Output
compare
output
PWM*
3
mode 1
output
⎯ PWM mode 2
output
⎯
Notes: 1. TIOCA4-B input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx.
2. IRQ2-A input when the ITS2 bit in ITSR is 0.
3. TIOCB4-B output disabled.
4. When using as PO4-B output, set PPGS in PFCR3 to 1 before other register setting.
5. When using as TIOCA4-B input/output, set TPUS in PFCR3 to 1 before other register
setting.
6. When using as TMO0-B output, set TMRS in PFCR3 to 1 before other register setting.