Datasheet

Section 10 I/O Ports
Page 562 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
TPU channel 3
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOA3 to IOA0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Other than
B'xx00
Other than B'xx00
CCLR2 to
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'001
B'001
Output function ⎯ Output
compare
output
⎯ PWM
*
3
mode
1 output
PWM mode 2
output
⎯
[Legend]
x: Don't care
Notes: 1. TIOCA3-A input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.
2. When used as the counter reset input pin for the TMR, the external reset should be
selected using the bits CCLR1 and CCLR0 in TCR_0 and TMRIS bit in TCCR_0 after
the TMRS bit in PFCR3 is set to 0.
3. TIOCB3 output disabled.
4. When using as PO0-A output, set PPGS in PFCR3 to 0 before other register setting.
5. When using as TIOCA3-A input/output, set TPUS in PFCR3 to 0 before other register
setting.
6. When using as TMRI0-A input, set TMRS in PFCR3 to 0 before other register setting.