Datasheet

Section 10 I/O Ports
R01UH0309EJ0500 Rev. 5.00 Page 561 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
TPU channel 4
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯ B'xx00 Other than B'xx00
CCLR1,
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'10
B'10
Output function ⎯ Output
compare
output
⎯ ⎯ PWM mode
2 output
⎯
[Legend]
x: Don't care
• P20/PO0-A/TIOCA3-A/TMRI0-A/PUPD+
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIOR H_3, and bits
CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL of the PPG, bit PULLUP_E in CTLR of
the USB, bits PPGS, TPUS and TMRS in PFCR3, and bit P20DDR.
PULLUP_E 0 1
TPU channel 3
settings
(1) in table
below
(2) in table below ⎯
P20DDR ⎯ 0 1 ⎯
NDER0 ⎯ ⎯ 0 1 ⎯
P20 input P20 output PO0-A output*
4
TIOCA3-A
output*
5
TIOCA3-A input*
1
*
5
Pin function
IRQ8-B-A input*
2
*
6
PUPD+ output