Datasheet

Section 10 I/O Ports
Page 558 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(2) Pin Functions of H8S/2454 Group
• P27/PO7/TIOCB5/SCL2
The pin function is switched as shown below according to the combination of the TPU channel
5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1
and CCLR0 in TCR_5), bit NDER7 in NDERL of PPG, bit ICE in ICCRA_2 of I
2
C, and bit
P27DDR.
ICE 0 1
TPU channel 5
settings
(1) in table
below
(2) in table below ⎯
P27DDR ⎯ 0 1 1 ⎯
NDER7 ⎯ ⎯ 0 1 ⎯
P27 input P27 output PO7 output SCL2 I/O*
2
Pin function TIOCB5 output
TIOCB5 input*
1
Notes: 1. TIOCB5 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1.
2. NMOS open-drain output regardless of P27ODR.
TPU channel 5
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯ B'xx00 Other than B'xx00
CCLR1,
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'10
B'10
Output function ⎯ Output
compare
output
⎯ ⎯ PWM mode
2 output
⎯
[Legend]
x: Don't care