Datasheet

Section 10 I/O Ports
R01UH0309EJ0500 Rev. 5.00 Page 553 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
TPU channel 5
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯ B'xx00 Other than B'xx00
CCLR1,
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'10
B'10
Output function ⎯ Output
compare
output
⎯ ⎯ PWM mode
2 output
⎯
[Legend]
x: Don't care
• P26/PO6/TIOCA5/IRQ14-B/SDA2/ADTRG1
The pin function is switched as shown below according to the combination of the TPU channel
5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1
and CCLR0 in TCR_5), bit NDER6 in NDERL of PPG, bits TRGS1, TRGS0, and EXTRGS in
ADCR_1 of ADC, bit ICE in ICCRA_2 of I
2
C, bit P26DDR, and bit ITS14 in ITSR of the
interrupt controller.
ICE 0 1
TPU channel 5
settings
(1) in table
below
(2) in table below ⎯
P26DDR ⎯ 0 1 1 ⎯
NDER6 ⎯ ⎯ 0 1 ⎯
P26 input P26 output PO6 output SDA2 I/O
*
5
TIOCA5 output
TIOCA5 input
*
1
IRQ14-B interrupt input
*
2
Pin function
ADTRG1 input*
4