Datasheet

Section 10 I/O Ports
Page 550 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
10.2.2 Port 2 Data Register (P2DR)
P2DR stores output data for the port 2 pins.
Bit Bit Name Initial Value R/W Description
7 P27DR 0 R/W
6 P26DR 0 R/W
5 P25DR 0 R/W
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
4 ⎯ 0 ⎯
3 ⎯ 0 ⎯
2 ⎯ 0 ⎯
1 ⎯ 0 ⎯
Bits 4 to 1 are reserved.
These bits are read as 0.
When written, the initial value should be written to.
0 P20DR 0 R/W Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
10.2.3 Port 2 Register (PORT2)
PORT2 shows the pin states of port 2. PORT2 cannot be modified.
Bit Bit Name Initial Value R/W Description
7 P27 ⎯* R
6 P26 ⎯* R
5 P25 ⎯* R
If this register is read while a P2DDR bit is set to 1,
the corresponding P2DR value is read. If this
register is read while a P2DDR bit is cleared to 0,
the corresponding pin state is read.
4 ⎯ Undefined ⎯
3 ⎯ Undefined ⎯
2 ⎯ Undefined ⎯
1 ⎯ Undefined ⎯
Bits 4 to 1 are reserved.
The read value is undefined.
0 P20 ⎯* R If this register is read while a P2DDR bit is set to 1,
the corresponding P2DR value is read. If this
register is read while a P2DDR bit is cleared to 0,
the corresponding pin state is read.
Note: * Determined by the states of pins P27 to P25 and P20.