Datasheet

Section 10 I/O Ports
R01UH0309EJ0500 Rev. 5.00 Page 527 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
• Modes 3 and 7 (EXPE = 0)
SSU settings (1) in table below (2) in table
below
(4) in table
below
(3) in table
below
EDRAKE 0 ⎯
TPU channel 2
settings
(1) in table
below
(2) in table below ⎯
P17DDR ⎯ 0 1 1 0
*
6
0
*
6
⎯
NDER15 ⎯ ⎯ 0 1 ⎯
P17
input
P17
output
PO15
output
TIOCB2
output
TIOCB2 input
*
1
Pin function
TCLKD input
*
2
SCS0-A
input
*
3
*
7
SCS0-A
I/O
*
5
*
7
SCS0-A
output
*
4
*
7
Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1.
2. TCLKD input when the setting for either TCR_0 or TCR_5 is TPSC2 to TPSC0 = B'111.
TCLKD input when channels 2 and 4 are set to phase counting mode.
3. When using as SCS0-A input, set SCS0S1 and SCS0S0 in PFCR5 to B'00 before other
register setting.
4. When using as SCS0-A output, set SCS0S1 and SCS0S0 in PFCR5 to B'00 before
other register setting.
5. When using as SCS0-A input/output, set SCS0S1 and SCS0S0 in PFCR5 to B'00
before other register setting.
6. P17DDR = 0 when the SSU pin is used as input.
7. Do not set up for SSU unless SCS0S1 and SCS0S0 = B'00 in PFCR5.
Use as I/O port, TPU or EXDMAC pin.
TPU channel 2
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯ B'xx00 Other than B'xx00
CCLR1,
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'10
B'10
Output function ⎯ Output
compare
output
⎯ ⎯ PWM mode
2 output
⎯