Datasheet

Section 9 Data Transfer Controller (DTC)
R01UH0309EJ0500 Rev. 5.00 Page 505 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
First data
transfer register
information
Second data
transfer register
information
Chain transfer
(counter = 0)
Upper 8 bits
of DAR
Input buffer
Input circuit
Figure 9.13 Chain Transfer when Counter = 0