Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 144 (20x20) 16-Bit 32 MHz I/O number 96

Section 9 Data Transfer Controller (DTC)

R01UH0309EJ0500 Rev. 5.00 Page 493 of 1408

Sep 24, 2012

H8S/2456, H8S/2456R, H8S/2454 Group

Table 9.3 Chain Transfer Conditions

1st Transfer 2nd Transfer

CHNE CHNS DISEL CR CHNE CHNS DISEL CR DTC Transfer

0 ⎯ 0 Not 0 ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer

0 ⎯ 0 0 ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer

0 ⎯ 1 ⎯ ⎯ ⎯ ⎯ ⎯ Interrupt request to CPU

1 0 ⎯ ⎯ 0 ⎯ 0 Not 0 Ends at 2nd transfer

0 ⎯ 0 0 Ends at 2nd transfer

0 ⎯ 1 ⎯ Interrupt request to CPU

1 1 0 Not 0 ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer

1 1 ⎯ 0 0 ⎯ 0 Not 0 Ends at 2nd transfer

0 ⎯ 0 0 Ends at 2nd transfer

0 ⎯ 1 ⎯ Interrupt request to CPU

1 1 1 Not 0 ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer

Interrupt request to CPU