Datasheet

Section 9 Data Transfer Controller (DTC)
R01UH0309EJ0500 Rev. 5.00 Page 487 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
9.4 Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF).
Register information should be located at the address that is multiple of four within the range.
Locating the register information in address space is shown in figure 9.3. Locate the MRA, SAR,
MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register
information. In the case of chain transfer, register information should be located in consecutive
areas as shown in figure 9.3 and the register information start address should be located at the
corresponding vector address to the activation source. Figure 9.4 shows correspondences between
the DTC vector address and register information. The DTC reads the start address of the register
information from the vector address set for each activation source, and then reads the register
information from that start address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[7:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420.
The configuration of the vector address is the same in both normal
*
and advanced modes, a 2-byte
unit being used in both cases. These two bytes specify the lower bits of the register information
start address.
Note: * Not available in this LSI.
MRAStart address of
register information
Register information
Register information
for second transfer
in case of chain
transfer
Chain transfer
Lower addresses
Four bytes
0123
SAR
MRB
DAR
CRA
CRB
MRA
SAR
MRB
DAR
CRA
CRB
Figure 9.3 Correspondence between DTC Vector Address and Register Information