Datasheet

Section 9 Data Transfer Controller (DTC)
Page 484 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
9.2.9 DTC Control Register (DTCCR)
DTCCR enables or disables DTC activation by software.
Bit Bit Name Initial Value R/W Description
7 SWDTE 0 R/W DTC Software Activation Enable
Setting this bit to 1 activates the DTC. Only 1 can
be written to this bit.
[Clearing conditions]
• When the DISEL bit is 0 and the specified
number of transfers have not ended
• When 0 is written to the DISEL bit after a
software-activated data transfer end interrupt
(SWDTEND) request has been sent to the
CPU.
When the DISEL bit is 1 and data transfer has
ended or when the specified number of transfers
have ended, this bit will not be cleared.
6 to 0 ⎯ All 0 R Reserved
These bits are always read as 0 and cannot be
modified.