Datasheet

Section 9 Data Transfer Controller (DTC)
R01UH0309EJ0500 Rev. 5.00 Page 481 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
9.2.2 DTC Mode Register B (MRB)
MRB selects the DTC operating mode.
Bit Bit Name Initial Value R/W Description
7 CHNE Undefined ⎯ DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to section 9.5.4,
Chain Transfer.
In data transfer with CHNE set to 1, determination
of the end of the specified number of transfers,
clearing of the activation source flag, and clearing
of DTCER is not performed.
6 DISEL Undefined ⎯ DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends.
When this bit is set to 0, a CPU interrupt request is
generated at the time when the specified number
of data transfer ends.
5 CHNS Undefined ⎯ DTC Chain Transfer Select
Specifies the chain transfer condition.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
4 to 0 ⎯ Undefined ⎯ Reserved
These bits have no effect on DTC operation, and
should always be written with 0.