Datasheet
Section 9 Data Transfer Controller (DTC)
Page 478 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
The DTC's register information is stored in the on-chip RAM. When the DTC is used, the RAME
bit in SYSCR and MSTP32 bit in RMMSTPCR must be set to 1 and 0, respectively. A 32-bit bus
connects the DTC to the on-chip RAM (1 Kbyte), enabling 32-bit/1-state reading and writing of
the DTC register information.
DTVECR
DTC On-chip RAM
MRA MRB
CRA
CRB
DAR
SAR
DTCCR
Interrupt
request
Interrupt controller
Internal address bus
DTC activation
request
Register information
CPU interrupt
request
Internal data bus
[Legend]
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERI:
DTVECR:
DTCCR:
DTC mode registers A and B
DTC transfer count registers A and B
DTC source address register
DTC destination address register
DTC enable registers A to I
DTC vector register
DTC control register
DTCERA
to
DTCERI
Control logic
Figure 9.1 Block Diagram of DTC