Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 472 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(4) Transfer Abort by NMI Interrupt
EXDMA transfer is aborted when an NMI interrupt is generated. The EDA bit is cleared to 0 in all
channels. In external request mode, EXDMA transfer is performed for all transfer requests for
which EDRAK has been output. In dual address mode, processing is executed for the write cycle
following the read cycle.
In block transfer mode, operation is aborted even in the middle of a block-size transfer. As the
transfer is halted midway through a block, the BEF bit in EDMDR is set to 1 to indicate that the
block transfer was not carried out normally.
When transfer is aborted, register values are retained, and as the address registers indicate the next
transfer addresses, transfer can be resumed by setting the EDA bit to 1 in EDMDR. If the BEF bit
is 1 in EDMDR, transfer can be resumed from midway through a block.
(5) Hardware Standby Mode and Reset Input
The EXDMAC is initialized in hardware standby mode and by a reset. EXDMA transfer is not
guaranteed in these cases.
8.4.13 Relationship between EXDMAC and Other Bus Masters
The read and write operations in an EXDMA transfer cycle are indivisible, and a refresh cycle,
external bus release cycle, or internal bus master (CPU, DTC, or DMAC) external space access
cycle never occurs between the two.
When read and write cycles occur consecutively, as in burst transfer or block transfer, a refresh or
external bus release state may be inserted after the write cycle. As the internal bus masters are of
lower priority than the EXDMAC, external space accesses by internal bus masters are not
executed until the EXDMAC releases the bus.
The EXDMAC releases the bus in the following cases:
1. When EXDMA transfer is performed in cycle steal mode
2. When switching to a different channel
3. When transfer ends in burst transfer mode
4. When transfer of one block ends in block transfer mode
5. When burst transfer or block transfer is performed with the BGUP bit in EDMDR set to 1
(however, the bus is not released between read and write cycles)