Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 470 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
φ pin EDREQ EDRAK ETEND Bus cycle
Other channel EDREQ Other channel EDRAK
Bus release
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
Last transfer
in block
Last transfer
in block
1-block-size transfer period 1-block-size transfer period
Other channel
EXDMA cycle
Bus release
Bus release
RepeatedRepeated
Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode
(Contention with Another Channel/Dual Address Mode/Low Level Sensing)