Datasheet
Section 8 EXDMA Controller (EXDMAC)
R01UH0309EJ0500 Rev. 5.00 Page 469 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
φ pin
EDREQ
EDRAK
Bus cycle
CPU
operation
EDACK
ETEND
1-block-size transfer period
1 bus cycle
CPU
cycle
CPU
cycle
External
space
External
space
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
External
space
External
space
External
space
External
space
External
space
External
space
1 bus cycle
1 bus cycle
Last transfer
in block
EXDMA
transfer cycle
EXDMA
transfer cycle
EXDMA
transfer cycle
EXDMA
transfer cycle
EXDMA
transfer cycle
EXDMA
transfer cycle
EXDMA
transfer cycle
Repeated
Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1)