Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 466 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
φ pin EDREQ EDRAK EDACK Bus cycle ETEND
Bus release Bus release
Last transfer
in block
1-block-size transfer period
Last block
Last transfer cycle3 cycles
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
Repeated Repeated
Bus release
Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode
(No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0)