Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0309EJ0500 Rev. 5.00 Page 461 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
φ pin
Bus cycle
Original
channel
EDACK
Original
channel
ETEND
Other
channel
transfer
request
(EDREQ)
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
1 cycleLast transfer
cycle
Other channel EXDMA cycle
Bus release
Bus
release
Bus
release
Figure 8.34 Auto Request/Burst Mode/Normal Transfer Mode
(Contention with Another Channel/Single Address Mode)