Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 460 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
φ pin
Bus cycle
CPU
operation
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
External
space
External
space
External
space
External
space
1 bus cycle 1 bus cycle
CPU cycle CPU cycle CPU cycle CPU cycle
Figure 8.32 Auto Request/Burst Mode/Normal Transfer Mode
(CPU Cycles/Dual Address Mode/BGUP = 1)
CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle
External
space
External
space
External
space
External
space
External
space
1 bus cycle
Last transfer cycle
φ pin
EDACK
Bus cycle
CPU
operation
ETEND
EXDMA
single cycle
EXDMA
single cycle
EXDMA
single cycle
EXDMA
single cycle
EXDMA
single cycle
Figure 8.33 Auto Request/Burst Mode/Normal Transfer Mode
(CPU Cycles/Single Address Mode/BGUP = 1)