Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0309EJ0500 Rev. 5.00 Page 459 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(2) Auto Request/Burst Mode/Normal Transfer Mode
When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three
cycles later. Once transfer is started, it continues (as a burst) until the transfer end condition is
satisfied.
If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another
bus master.
Transfer requests for other channels are held pending until the end of transfer on the current
channel.
Figures 8.31 to 8.34 show operation timing examples for various conditions.
φ pin
ETEND
Bus cycle
CPU
operation
EDA bit
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
External
space
External
space
External
space
01
Repeated
Last transfer cycle
CPU cycle CPU cycle CPU cycle
Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode
(CPU Cycles/Dual Address Mode/BGUP = 0)