Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 454 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
EXDMA write
HWR
ETEND
Address bus
φ
Bus release Bus release Bus
release
Last transfer cycle
EDACK
Bus release
EXDMA writeEXDMA write
LWR
Figure 8.25 Example of Single Address Mode (Word Write) Transfer
After one byte or word has been transferred in response to one transfer request, the bus is released.
While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.