Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0309EJ0500 Rev. 5.00 Page 453 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
After one byte or word has been transferred in response to one transfer request, the bus is released.
While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.
(2) Single Address Mode (Write)
Figure 8.24 shows an example of transfer when ETEND output is enabled, and byte-size, single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
HWR
ETEND
Address bus
φ
Bus release Bus release Bus release
Last
transfer
cycle
EXDMA write
EDACK
EXDMA writeEXDMA write
EXDMA write
Bus releaseBus release
LWR
Figure 8.24 Example of Single Address Mode (Byte Write) Transfer
Figure 8.25 shows an example of transfer when ETEND output is enabled, and word-size, single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.