Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 448 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(4) EDREQ Pin Falling Edge Activation Timing
Figure 8.18 shows an example of normal mode transfer activated by the EDREQ pin falling edge.
EXDMA
read
EXDMA
write
Address bus
φ
EDREQ
Write Idle
Bus release
Transfer
destination
EXDMA control
Channel
Write Idle
Transfer source Transfer source
Bus release
EXDMA
read
EXDMA
write
Bus release
Request
Request
[1] [3]
[2] [4] [5] [6] [7]
Acceptance
resumed
Acceptance
resumed
Read Read
Idle
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle start; EDREQ pin high level sampling is started at rise of φ.
[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Transfer
destination
Request clearance period Request clearance period
Minimum 3 cycles
Minimum 3 cycles
Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ
pin high level sampling is completed by the end of the EXDMA write cycle, acceptance resumes
after the end of the write cycle, and EDREQ pin low level sampling is performed again; this
sequence of operations is repeated until the end of the transfer.
Figure 8.19 shows an example of block transfer mode transfer activated by the EDREQ pin falling
edge.