Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0309EJ0500 Rev. 5.00 Page 447 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(3) Block Transfer Mode (Cycle Steal Mode)
Figure 8.17 shows an example of transfer when ETEND output is enabled, and word-size, block
transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to
external 16-bit, 2-state access space.
One block is transferred in response to one transfer request, and after the transfer, the bus is
released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.
EXDMA
read
RD
HWR
ETEND
LWR
EXDMA
write
Address bus
φ
Bus
release
Bus
release
Bus
release
Last block transfer
EXDMA
read
Block transfer
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer