Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 444 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Figure 8.14 shows examples of transfer timing in cases that include auto request cycle steal mode.
Channel 2 Channel 2 Channel 2 Channel 3 Channel 3
Bus
Conditions (1)
Channel 2: Auto request, cycle steal mode
Channel 3: External request, cycle steal mode, low level activation
Channel 2
EDA bit
Channel 3/
EDREQ3 pin
Channel 3 Channel 3 Channel 2 Channel 2Channel 3
Channel 2
Bus
Conditions (2)
Channel 2: External request, cycle steal mode, low level activation
Channel 3: Auto request, cycle steal mode
Channel 2/
EDREQ2 pin
Channel 2
EDA bit
Channel 3 Channel 3 Channel 2 Channel 3
Channel 2
Bus
Conditions (3)
Channel 2: Auto request, cycle steal mode
Channel 3: Auto request, cycle steal mode
*
: Bus release
Channel 2
EDA bit
Channel 3
EDA bit
*
*
**** *
*** *
** * *
Figure 8.14 Examples of Channel Priority Timing