Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0309EJ0500 Rev. 5.00 Page 443 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(2) Transfer Requests from Multiple Channels in Auto Request Cycle Steal Mode
If transfer requests for different channels are issued during a transfer in auto request cycle steal
mode, the operation depends on the channel priority. If the channel that made the transfer request
is of higher priority than the channel currently performing transfer, the channel that made the
transfer request is selected.
If the channel that made the transfer request is of lower priority than the channel currently
performing transfer, that channel's transfer request is held pending, and the currently transferring
channel remains selected.
The selected channel begins transfer after the currently transferring channel releases the bus. If
there is a bus request from a bus master other than the EXDMAC at this time, a cycle for the other
bus master is initiated. If there is no other bus request, the bus is released for one cycle.