Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 442 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(1) Transfer Requests from Multiple Channels (Except Auto Request Cycle Steal Mode)
If transfer requests for different channels are issued during a transfer operation, the highest-
priority channel (excluding the currently transferring channel) is selected. The selected channel
begins transfer after the currently transferring channel releases the bus. If there is a bus request
from a bus master other than the EXDMAC at this time, a cycle for the other bus master is
initiated. If there is no other bus request, the bus is released for one cycle.
Channel switching does not take place during a burst transfer or a block transfer of a single block.
Figure 8.13 shows a case in which transfer requests for channels 2 and 3 are issued
simultaneously. The example shown in the figure illustrates the handling of external requests in
the cycle steal mode.
Channel 2 transfer
φ
Idle
Bus
release
Address bus
EXDMA control
Channel 3 transfer
Channel 2 Channel 3
Channel 2
Request
held
Selected
Channel 3
Request cleared
Request cleared
Bus
release
Channel 2
Channel 3
Figure 8.13 Example of Channel Priority Timing