Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0309EJ0500 Rev. 5.00 Page 441 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(5) BEF Bit in EDMDR
In block transfer mode, the specified number of transfers (equivalent to the block size) is
performed in response to a single transfer request. To ensure that the correct number of transfers is
carried out, a block-size transfer is always executed, except in the event of a reset, transition to
standby mode, or generation of an NMI interrupt.
If an NMI interrupt is generated during block transfer, operation is halted midway through a
block-size transfer and the EDA bit is cleared to 0, terminating the transfer operation. In this case
the BEF bit, which indicates the occurrence of an error during block transfer, is set to 1.
(6) IRF Bit in EDMDR
The IRF bit in EDMDR is set to 1 when an interrupt request source occurs. If the EDIE bit in
EDMDR is 1 at this time, an interrupt is requested.
The timing for setting the IRF bit to 1 is when the EDA bit in EDMDR is cleared to 0 and transfer
ends following the end of the EXDMA transfer bus cycle in which the source generating the
interrupt occurred.
If the EDA bit is set to 1 and transfer is resumed during interrupt handling, the IRF bit is
automatically cleared to 0 and the interrupt request is cleared.
For details on interrupts, see section 8.5, Interrupt Sources.
8.4.8 Channel Priority Order
The priority order of the EXDMAC channels is: channel 2 > channel 3. Table 8.3 shows the
EXDMAC channel priority order.
Table 8.3 EXDMAC Channel Priority Order
Channel Priority
Channel 2
High
Channel 3
Low
If transfer requests occur simultaneously for a number of channels, the highest-priority channel
according to the priority order in table 8.3 is selected for transfer.