Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 440 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
When transfer is halted by writing 0 to the EDA bit, the EDA bit remains at 1 during the EXDMA
transfer period. In block transfer mode, since a block-size transfer is carried out without
interruption, the EDA bit remains at 1 from the time 0 is written to it until the end of the current
block-size transfer.
In burst mode, transfer is halted for up to three EXDMA transfers following the bus cycle in
which 0 is written to the EDA bit. The EDA bit remains set to 1 from the time of the 0-write until
the end of the last DMA cycle.
Writes (except to the EDA bit) are prohibited to registers of a channel for which the EDA bit is set
to 1. When changing register settings after a 0-write to the EDA bit, it is necessary to confirm that
the EDA bit has been cleared to 0.
Figure 8.12 shows the procedure for changing register settings in an operating channel.
Read EDA bit
Write 0 to EDA bit
Change register settings
EDA bit = 0?
[1]
[2]
[3]
[4]
[1] Write 0 to the EDA bit in EDMDR.
[2] Read the EDA bit.
[3] Confirm that EDA = 0. If EDA = 1, this
indicates that EXDMA transfer is in progress.
[4] Write the required set values to the registers.
No
Yes
Changing register settings
in operating channel
Register setting
changes completed
Figure 8.12 Procedure for Changing Register Settings in Operating Channel