Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 438 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
When EDDAR is read during a transfer operation, a longword access must be used. During a
transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the
correct values may not be read if the upper and lower words are read separately. In a longword
access, the EXDMAC buffers the EDDAR value to ensure that the correct value is output.
Do not write to EDDAR for a channel on which a transfer operation is in progress.
(3) EXDMA Transfer Count Register (EDTCR)
When an EXDMA transfer is performed, the value in EDTCR is decremented by 1. However,
when the EDTCR value is 0, transfers are not counted and the EDTCR value does not change.
EDTCR functions differently in block transfer mode. The upper 8 bits, EDTCR[23:16], are used to
specify the block size, and their value does not change. The lower 16 bits, EDTCR[15:0], function
as a transfer counter, the value of which is decremented by 1 when an EXDMA transfer is
performed. However, when the EDTCR[15:0] value is 0, transfers are not counted and the
EDTCR[15:0] value does not change.
In normal transfer mode, all of the lower 24 bits of EDTCR may change, so when EDTCR is read
by the CPU during EXDMA transfer, a longword access must be used. During a transfer
operation, EDTCR may be updated without regard to accesses from the CPU, and the correct
values may not be read if the upper and lower words are read separately. In a longword access, the
EXDMAC buffers the EDTCR value to ensure that the correct value is output.
In block transfer mode, the upper 8 bits are never updated, so there is no problem with using word
access.
Do not write to EDTCR for a channel on which a transfer operation is in progress. If there is
contention between an address update associated with EXDMA transfer and a write by the CPU,
the CPU write has priority.
In the event of contention between an EDTCR update from 1 to 0 and a write (of a nonzero value)
by the CPU, the CPU write value has priority as the EDTCR value, but transfer is terminated.
Transfer does not end if the CPU writes 0 to EDTCR.