Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0309EJ0500 Rev. 5.00 Page 433 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
CPUCPU CPU EXDMAC EXDMAC EXDMAC CPU
Bus cycle
EDRAK
ETEND
EDREQ
CPU cycle not generated
One-block transfer cycle
Transfer conditions:
· Single address mode
· BGUP = 0
· Block size (EDTCR[23:16]) = 3
Figure 8.8 Example of Timing in Block Transfer Mode