Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0309EJ0500 Rev. 5.00 Page 427 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
EXDMA cycle
EDSAR
Address to external memory space
RD signal to external memory space
Data output from external memory
Address bus
φ
RD
WR
EDACK
ETEND
Data bus
EXDMA cycle
EDDAR
Address to external memory space
WR signal to external memory space
Address bus
φ
Transfer from external memory to external device with DACK
Transfer from external device with DACK to external memory
RD
WR
EDACK
ETEND
Data bus
Data output from external device
with DACK
Figure 8.4 Example of Timing in Single Address Mode