Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 426 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Figure 8.3 shows the data flow in single address mode, and figure 8.4 shows an example of the
timing.
Microcomputer
Data flow
External
address bus
External
data bus
EXDMAC
EDACK
EDREQ
External
memory
External device
with DACK
Figure 8.3 Data Flow in Single Address Mode