Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0309EJ0500 Rev. 5.00 Page 425 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Figure 8.2 shows an example of the timing in dual address mode.
A
ddress bus
φ
RD
WR
ETEND
EXDMA
read cycle
EXDMA
write cycle
EDSAR EDDAR
Figure 8.2 Example of Timing in Dual Address Mode
(2) Single Address Mode
In single address mode, the EDACK signal is used instead of the source or destination address
register to transfer data directly between an external device and external memory. In this mode,
the EXDMAC accesses the transfer source or transfer destination external device by outputting the
external I/O strobe signal (EDACK), and at the same time accesses the other external device in the
transfer by outputting an address. In this way, EXDMA transfer can be executed in one bus cycle.
In the example of transfer between external memory and an external device with DACK shown in
figure 8.3, data is output to the data bus by the external device and written to external memory in
the same bus cycle.
The transfer direction, that is whether the external device with DACK is the transfer source or
transfer destination, can be specified with the SDIR bit in EDMDR. Transfer is performed from
the external memory (EDSAR) to the external device with DACK when SDIR = 0, and from the
external device with DACK to the external memory (EDDAR) when SDIR = 1.
The setting in the source or destination address register not used in the transfer is ignored.
The EDACK pin becomes valid automatically when single address mode is selected. The EDACK
pin is active-low. ETEND pin output can be enabled or disabled by means of the ETENDE bit in
EDMDR. ETEND is output for one bus cycle.