Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0309EJ0500 Rev. 5.00 Page 419 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
8.3.5 EXDMA Address Control Register (EDACR)
EDACR specifies address register incrementing/decrementing and use of the repeat area function.
Bit Bit Name Initial Value R/W Description
15
14
SAT1
SAT0
0
0
R/W
R/W
Source Address Update Mode
These bits specify incrementing/decrementing of
the transfer source address (EDSAR). When an
external device with DACK is designated as the
transfer source in single address mode, the
specification by these bits is ignored.
0x: Fixed
10: Incremented (+1 in byte transfer, +2 in word
transfer)
11: Decremented (–1 in byte transfer, –2 in word
transfer)
13 SARIE 0 R/W Source Address Repeat Interrupt Enable
When this bit is set to 1, in the event of source
address repeat area overflow, the IRF bit is set to
1 and the EDA bit cleared to 0 in EDMDR, and
transfer is terminated. If the EDIE bit in EDMDR is
1 when the IRF bit in EDMDR is set to 1, an
interrupt request is sent to the CPU.
When used together with block transfer mode, a
source address repeat interrupt is requested at the
end of a block-size transfer. If the EDA bit is set to
1 in EDMDR for the channel on which transfer is
terminated by a source address repeat interrupt,
transfer can be resumed from the state in which it
ended. If a source address repeat area has not
been designated, this bit is ignored.
0: Source address repeat interrupt is not
requested
1: When source address repeat area overflow
occurs, the IRF bit in EDMDR is set to 1 and an
interrupt is requested