Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 408 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Figure 8.1 shows a block diagram of the EXDMAC.
Bus controller
Internal data bus
Interrupt request
signals to CPU
for individual
channels
External pins
EDMDR
EDACR
EDTCR
EDDAR
EDSAR
Processor
Address buffer
Data buffer
Control logic
Module data bus
EDREQ
EDRAK
ETEND
EDACK
[Legend]
EDSAR: EXDMA source address register
EDDAR: EXDMA destination address register
EDTCR: EXDMA transfer count register
EDMDR: EXDMA mode control register
EDACR: EXDMA address control register
Figure 8.1 Block Diagram of EXDMAC