Datasheet

Section 7 DMA Controller (DMAC)
Page 402 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
7.7 Usage Notes
(1) DMAC Register Access during Operation
Except for forced termination of the DMAC, the operating (including transfer waiting state)
channel setting should not be changed. The operating channel setting should only be changed
when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
• DMAC control starts one cycle before the bus cycle, with output of the internal address.
Consequently, MAR is updated in the bus cycle before DMA transfer. Figure 7.39 shows an
example of the update timing for DMAC registers in dual address transfer mode.
[1] Transfer source address register MAR operation (incremented/decremented/fixed)
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
[2] Transfer destination address register MAR operation (incremented/decremented/fixed)
[2']Transfer destination address register MAR operation (incremented/decremented/fixed)
Block transfer counter ETCR operation (decremented, in last transfer cycle of
a block in block transfer mode)
[3] Transfer address register MAR restore operation (in block or repeat transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
Note: In single address transfer mode, the update timing is the same as [1].
The MAR operation is post-incrementing/decrementing of the DMA internal address value.
DMA transfer cycle
DMA read
DMA read
DMA write
DMA write
DMA
dead
DMA Internal
address
φ
DMA control
DMA register
operation
DMA last transfer cycle
Transfer
destination
Transfer
destination
Transfer
source
Transfer
source
Idle
Idle
IdleRead
Read
Dead
Write
Write
[3]
[2'][2]
[1]
[1]
Figure 7.39 DMAC Register Update Timing