Datasheet

Section 7 DMA Controller (DMAC)
R01UH0309EJ0500 Rev. 5.00 Page 401 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
7.6 Interrupt Sources
The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12
shows the interrupt sources and their priority order.
Table 7.12 Interrupt Sources and Priority Order
Interrupt Source
Interrupt Name Short Address Mode Full Address Mode
Interrupt
Priority Order
DMTEND0A Interrupt due to end of
transfer on channel 0A
Interrupt due to end of
transfer on channel 0
High
DMTEND0B Interrupt due to end of
transfer on channel 0B
Interrupt due to break in
transfer on channel 0
DMTEND1A Interrupt due to end of
transfer on channel 1A
Interrupt due to end of
transfer on channel 1
DMTEND1B Interrupt due to end of
transfer on channel 1B
Interrupt due to break in
transfer on channel 1 Low
Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCRL for
the corresponding channel in DMABCRL, and interrupts from each source are sent to the interrupt
controller independently. The priority of transfer end interrupts on each channel is decided by the
interrupt controller, as shown in table 7.12.
Figure 7.38 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is
always generated when the DTIE bit is set to 1 while the DTE bit in DMABCRL is cleared to 0.
DTE/
DTME
DTIE
Transfer end/transfe
r
break interrupt
Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt
In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0
while the DTIE bit is set to 1. In both short address mode and full address mode, DMABCR
should be set so as to prevent the occurrence of a combination that constitutes a condition for
interrupt generation during setting.