Datasheet

Section 7 DMA Controller (DMAC)
Page 396 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released, the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the
channel will not be changed until the end of the transfer. Figure 7.34 shows a transfer example in
which transfer requests are issued simultaneously for channels 0A, 0B, and 1.
DMA read DMA write DMA read DMA write DMA read DMA write
DMA
read
A
ddress bus
φ
RD
HWR
LWR
DMA control
Channel 0A
Channel 0B
Channel 1
Idle Write
Idle Read Write Idle Read Write Read
Request
hold
Request
hold
Bus
release
Channel 0A
transfer
Bus
release
Channel 0B
transfer
Channel 1 transfer
Bus
release
Re
quest
hold
Read
Selection
Non-
selection
Selection
Request clear
Request clear
Request clear
Figure 7.34 Example of Multi-Channel Transfer