Datasheet

Section 7 DMA Controller (DMAC)
Page 390 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
DMA write
A
ddress bus
φ
DMA write DMA write
DMA
dead
HWR
TEND
DACK
Bus
release
LWR
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 7.29 Example of Single Address Mode Transfer (Word Write)
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.