Datasheet

Section 7 DMA Controller (DMAC)
R01UH0309EJ0500 Rev. 5.00 Page 389 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(2) Single Address Mode (Write)
Figure 7.28 shows a transfer example in which TEND output is enabled and byte-size single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
DMA write
A
ddress bus
φ
DMA
dead
HWR
DACK
TEND
Bus
release
LWR
DMA write DMA write DMA write
Bus
release
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 7.28 Example of Single Address Mode Transfer (Byte Write)
Figure 7.29 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.