Datasheet

Section 7 DMA Controller (DMAC)
R01UH0309EJ0500 Rev. 5.00 Page 387 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
7.5.10 DMA Transfer (Single Address Mode) Bus Cycles
(1) Single Address Mode (Read)
Figure 7.26 shows a transfer example in which TEND output is enabled and byte-size single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
DMA read
A
ddress bus
φ
DMA
dead
RD
DACK
TEND
Bus
release
DMA read DMA read DMA read
Bus
release
Bus
release
Bus
release
Bus
releas
e
Last transfer
cycle
Figure 7.26 Example of Single Address Mode Transfer (Byte Read)
Figure 7.27 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.