Datasheet

Section 7 DMA Controller (DMAC)
Page 386 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Figure 7.25 shows an example of block transfer mode transfer activated by DREQ pin low level.
DMA
read
DMA
write
Address
bus
φ
DREQ
Idle Write
Bus release
DMA
control
Channel
Write
Transfer source
Request
[1] [3][2] [4] [6][5] [7]
Acceptance resumes
DMA
dead
Bus
release
DMA
read
DMA
write
DMA
dead
Bus
release
1 block transfer
IdleDead Dead
1 block transfer
Acceptance resumes
Request
Minimum
of 2 cycles
Minimum
of 2 cycles
Transfer source
Read
Request clear period
Read
Request clear period
Transfer destination
Transfer destination
Idle
[1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the dead cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is hel
d.)
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.