Datasheet

Section 7 DMA Controller (DMAC)
R01UH0309EJ0500 Rev. 5.00 Page 381 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(4) Full Address Mode (Block Transfer Mode)
Figure 7.21 shows a transfer example in which TEND output is enabled and word-size full address
mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to
external 16-bit, 2-state access space.
DMA
read
A
ddress bus
φ
RD
LWR
TEND
HWR
Bus release Block transfer Last block transfer
DMA
write
DMA
read
DMA
write
DMA
dead
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
Bus
release
Bus release
Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)
A one-block transfer is performed for a single transfer request, and after the transfer the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one-
state DMA dead cycle is inserted after the DMA write cycle. Even if an NMI interrupt is
generated during data transfer, block transfer operation is not affected until data transfer for one
block has ended.