Datasheet

Section 7 DMA Controller (DMAC)
R01UH0309EJ0500 Rev. 5.00 Page 379 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(2) Full Address Mode (Cycle Steal Mode)
Figure 7.19 shows a transfer example in which TEND output is enabled and word-size full address
mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to
external 16-bit, 2-state access space.
DMA
read
A
ddress bus
φ
RD
LWR
TEND
HWR
Bus release Last transfer
cycle
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
Bus release Bus release Bus
release
Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal)
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one bus cycle is executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.