Datasheet

Section 7 DMA Controller (DMAC)
R01UH0309EJ0500 Rev. 5.00 Page 377 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
7.5.8 Basic Bus Cycles
An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, word-
size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the
bus is transferred from the CPU to the DMAC, a source address read and destination address write
are performed. The bus is not released in response to another bus request, etc., between these read
and write operations. As like CPU cycles, DMA cycles conform to the bus controller settings.
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
A
ddress bus
φ
DMAC cycle (1-word transfer)
RD
LWR
HWR
Source
address
Destination address
CPU cycleCPU cycle
T
1
T
2
T
3
T
1
T
2
T
3
T
1
T
2
Figure 7.17 Example of DMA Transfer Bus Timing