Datasheet

Section 7 DMA Controller (DMAC)
Page 372 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Figure 7.13 illustrates operation in block transfer mode when MARB is designated as a block area.
A
ddress T
A
A
ddress B
A
Transfer
Address T
B
Address B
B
1st block
2nd block
Nth block
Block area
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Legend:
Address
Address
Address
Address
Where :
= L
A
= L
B
= L
A
+ SAIDE · (–1)
SAID
· (2
DTSZ
· (M·N – 1))
= L
B
+ DAIDE · (–1)
DAID
· (2
DTSZ
· (N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRB
= Value set in ETCRAH and ETCRAL
T
A
T
B
B
A
B
B
L
A
L
B
N
M
Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0)